1. Technical Field
The disclosure relates generally to integrated circuit (IC) design and, more particularly, to power gating logic cones.
2. Background Art
During integrated circuit (IC) operation, not all logic cones (i.e., sets of circuitry), within an IC are always powered up. For example, some logic cones may not be used for certain tasks and thus may be powered down to save energy and to make the IC perform better. Whenever a particular logic cone is powered up, there is almost always some sort of power dissipation occurring in other logic cones within the same voltage island. The power dissipation is a concern especially due to power density issues. Hence, it is advantageous to reduce power and, specifically, to reduce leakage power by power gating a logic cone. Power gating is the action of selecting a piece (cone) of logic, turning off the voltage to the logic gates of the logic cone to effectively save power, and fencing the logic cone output(s) so that when the logic cone is not powered the output(s) goes to a known state. The fencing of the logic cone output(s) prevents logic faults in other downstream logic cones. Current approaches of power gating typically use a manual process in selecting the logic cones to be power gated and a manual process to create the logic that controls the voltage island. The typical power gating is usually done in a high-level description language (HDL, VHDL or Verilog). This technique, however, leaves many non-power gated logic cones unnecessarily leaking power. Hence, it is desirable to automatically power gate logic cones and to maximize the amount of logic cones power gated to minimize leakage and save energy.